1. Field of the Invention
The present invention relates to reliable semiconductor via structures, and more particularly, the present invention relates to techniques for converting silicon dioxide layer regions within via hole walls into moisture repellant hydrophobic layer regions.
2. Description of the Related Art
In the fabrication of semiconductor devices, various layers are provided with conductive material, such as metal lines. The metal lines are commonly formed over successive insulating dielectric layers. Accordingly, it is generally necessary to electrically interconnect the metal lines between the dielectric layers. To accomplish this, vias (or via holes) are formed through the dielectric layers to electrically interconnect selected metal lines or features.
Spin on glass material (xe2x80x9cSOG materialxe2x80x9d) is used for some of the dielectric layers. For example, so-called xe2x80x9ctruexe2x80x9d SOG materials, such as that sold under the brand name xe2x80x9cLSU 418,xe2x80x9d which is available from Allied Signal, Inc. of Sunnyvale, Calif., is used because it has a low k characteristic (e.g., dielectric constant less than 4.0, which is common for silicon dioxide). Many xe2x80x9cSOG-likexe2x80x9d materials also have a low k characteristic. The SOG-like materials may, for example, be spin coated or result from vapor deposition using methyl silane and hydrogen peroxide chemistry. However, both the true SOG materials and the SOG-like materials oxidize during and after an operation known as ashing. Ashing is commonly performed to remove a photoresist layer that has been spin coated over the SOG material to facilitate patterning operations. Unfortunately, the oxidized SOG materials are known to absorb too much moisture from the atmosphere, in that during later operations (such as, for example, during metal deposition), the absorbed moisture outgasses causing poisoning of the vias. Such poisoning prevents adequate electrical connections from being made, e.g., between the opposite metal layers which are to be interconnected by way of the conductive material in the vias.
Unfortunately, prior art attempts to reduce the amount of the moisture retained by the oxidized SOG materials have not been successful. For example, if thermal outgassing is performed at a high enough temperatures to remove adequate amounts of the moisture (e.g., at about 700 degrees C.) from the oxidized SOG materials, significant problems result. These high outgassing temperatures are generally considered too excessive for the metal layers to withstand without causing damage (e.g., metal layers of aluminum may deform). Also, the SOG material is not stable at the high outgassing temperatures. If lower temperatures are used in an attempt to reduce the moisture retained by the oxidized SOG materials (e.g., at 400 to 450 degrees C. in a PVD chamber), although the metal lines may not be damaged by the temperature, not enough of the moisture is removed. The remaining moisture then outgasses during later attempts to deposit via coating/filling materials such as titanium nitride (TiN) and tungsten (W) metal layers (which are commonly used for the conductive vias), and such outgassing prevents proper continuous deposition of these metal layers in the internal via walls. For example, the outgassing moisture may prevent tungsten from being deposited on the walls of the via, and the TiN will tend to deposit discontinuously (e.g., in separate random groups), rather than in a complete conductive layer.
To facilitate this discussion, FIG. 1A shows a semiconductor structure including a substrate 101 supporting a first conductor 102, such as a metal line, which is to be in contact with a second conductor 103, such as a conductive layer of titanium nitride shown in FIG. 1C. Deposited on the substrate 101 is a layer 104 of SOG material, which may include both true SOG materials, materials having a SOG-like characteristic, and other organic low-K dielectric materials. Accordingly, such characteristic includes having a low dielectric constant (K), and oxidizing during photoresist ashing to form a surface layer 106 of silicon dioxide. After deposition of a silicon dioxide layer 107 on the layer 104 of SOG material, a via hole 109 is formed through the silicon dioxide layer 107 and through the SOG material layer 104 to expose the metal 102 as shown in FIG. 1A.
Between the etching operation and a subsequent deposition operation, a semiconductor structure 111 defined by the substrate 101 and the layers 102, 104, and 107, is exposed to oxygen in the atmosphere. The oxygen thus causes the inner wall surface of the via hole 109 to oxidize and form the surface layer 106. As described above, the surface layer 106 is very porous, is prone to collect moisture, and upon being heated, releases gaseous moisture.
The effect of the release of the moisture is shown in FIG. 1C, which depicts operations intended to deposit a layer 103 of titanium nitride under a layer 114 of tungsten. The purpose of the titanium nitride layer 103 is to electrically interconnect the first conductor 102 to the tungsten layer 114. However, FIG. 1C shows arrows 116 depicting moisture being outgassed from the surface layer 106 during the deposition of the titanium nitride layer 103. The outgassed moisture prevents the layer 103 of titanium nitride from being continuous, as illustrated by the spaced pieces 103a of titanium nitride. It may be understood, then, that the word xe2x80x9clayerxe2x80x9d in the phrase xe2x80x9clayer 103xe2x80x9d denotes the desired form of the titanium nitride, whereas the actual form of the prior art titanium nitride layer is discontinuous as shown in FIG. 1C. Because the pieces 103a are spaced, the desired electrical interconnection from the metal 102 to the tungsten 114 is not achieved.
Moreover, when an attempt is made to deposit the tungsten layer 114 after the titanium nitride pieces 103a, the tungsten layer 114 tends to stop short of filling the via, leaving a void 119 shown in FIGS. 1C and 1D. The void 119 is filled with neither titanium nitride nor tungsten, such that there is a high likelihood that there will be no electrical conductivity from the metal 102 to the tungsten layer 114.
In view of the forgoing, there is an unfilled need for a reliable semiconductor via structure, and a method of making reliable via structures to prevent outgassing problems and associated via hole voids.
Broadly speaking, the present invention fills these needs by providing improved semiconductor device via structures having an inner hydrophobic wall surface layer to prevent the aforementioned moisture absorption and subsequent outgassing. Such via structures are made using techniques for converting a silicon dioxide inner wall layer into the desirable hydrophobic layer, thus preventing the failure inducing voids in the via structures. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method of making a via hole in a semiconductor structure is disclosed. The via hole has a surface layer of hydrophobic material, and includes an outer layer of a material having a characteristic of SOG materials. The characteristic is that the outer layer oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole. In the method, an operation is performed after the ashing. The operation includes performing a chemical dehydroxylation operation on the surface layer of silicon dioxide to convert the surface layer of silicon dioxide to the surface layer of hydrophobic material. To achieve this, the semiconductor structure is placed in a closed process chamber, and then, a halogen compound is admitted into the process chamber to facilitate the chemical dehydroxylation operation. In this embodiment, the halogen compound is selected from either NH4F, other gaseous combination including fluorine, or CCl4.
In an other embodiment, a method of malting a via hole in a semiconductor device is disclosed. The method includes defining a via hole having a wall surface that at least partially has a characteristic of spin on glass materials. The characteristic being that the wall surface oxidizes during a photoresist ashing operation and the oxidizing converts the wall surface into a silicon dioxide skin. The method then includes placing the semiconductor device in a process chamber. Once the semiconductor device is placed in the process chamber, the method includes introducing a halogen gas into the process chamber to cause a chemical dehydroxylation of the silicon dioxide skin to thereby convert the silicon dioxide skin into a hydrophobic material skin, such that the hydrophobic skin is part of the wall surface of the via hole.
In still another embodiment, a semiconductor via structure that is configured to be defined through an inter-metal dielectric is disclosed. The structure includes a first conductive pattern element. A layer of SOG material formed over the first conductive pattern element. The layer of SOG material having a via hole defined therethrough, such that the via hole defines a path to the first conductive pattern element. The via hole has a via wall surface that is defined along the SOG material that extends to the first conductive pattern element, and the via wall surface has a hydrophobic material layer. In this embodiment, the hydrophobic material layer is a reaction product of silicon dioxide and a halogen compound. The halogen compound may be NH4F or CCl4, and when the CCl4 is used, the via hole fill material that will be in contact with the hydrophobic material layer is preferably copper.
As an advantage of each of such embodiments, no high temperature outgassing is required to avoid the disadvantages of the oxidized SOG layer, e.g., the silicon dioxide layer that is formed in the SOG after typical ashing operations. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.